1. Field of the Invention
The present invention relates, generally, to a multilayered chip capacitor (MLCC), and, more particularly, to a thin MLCC having excellent properties, which is suitable for embedding in a printed circuit board (PCB), and a PCB having an embedded MLCC.
2. Description of the Related Art
In general, an MLCC has a structure composed of a plurality of dielectric layers and a plurality of internal electrodes interposed between the dielectric layers. The MLCC, which is advantageous because it has a small size, a high capacitance and easy mountability, is widely applied to various electronic devices.
Recently, to decrease the overall package size and improve performance, the MLCC has been used in the state of being embedded in PCBs for memory cards, PC main boards and various RF modules. Such an MLCC is described with reference to a conventional MLCC shown in FIGS. 1a and 1b. 
FIGS. 1a and 1b are a schematic perspective view and a side sectional view, respectively, showing a conventional thin capacitor.
As shown in FIGS. 1a and 1b, a conventional MLCC 10 includes a capacitor body 11 formed by stacking a plurality of dielectric layers. First and second internal electrodes 12 and 13 are alternately formed on the plurality of dielectric layers. In addition, the first and second internal electrodes 12 and 13 face other second and first internal electrodes 13 and 12 with one of the plurality of dielectric layers interposed therebetween, and are connected, respectively, to first and second external electrodes formed on both side surfaces of the capacitor body 11.
Typically, since the first and second external electrodes 14 and 15 are manufactured in such a way that both side surfaces of the capacitor body 11 are dipped into a metal paste, they may be formed to extend the other surfaces neighboring the side surfaces of the capacitor body 11. In particular, when the above MLCC 10 is embedded in the PCB, the regions of the external electrodes, which extend the top and bottom surfaces of the capacitor body 11, allow the external electrodes of the capacitor to be connected to conductive via holes or conductive lines of the PCB.
Turning now to FIG. 2a, there is illustrated a PCB 20 in which the MLCC 10 of FIG. 1a has been embedded. The PCB 20 is composed of three layers 21a, 21b and 21c, on which predetermined conductive lines 22a, 22b and 22c are formed. A cavity C is formed in the middle layer 21b of the PCB 20, and the MLCC 10 is mounted in the cavity C. As such, the conductive line 22a to which chip components (not shown) are mounted, along with the conductive line 22b of the other layer 21b, is connected to the regions of the first external electrodes 14 positioned on the top surface of the capacitor 10 through the conductive via holes 23a and 23b. Also, the ground conductive line 22c is connected to the regions of the second external electrodes 15 positioned on the bottom surface of the capacitor 10 by soldering.
As is apparent from the equivalent circuit diagram of FIG. 1c, the MLCC 10 has not only capacitance Cs, which is an actual value, but also equivalent series resistance (ESR) Rs and insulation resistance Rp due to resistance loss of the dielectric layer and resistance loss of the electrode layer, and parasitic capacitance Cp and equivalent series inductance (ESL) Ls.
With the aim of easily embedding such an MLCC 10 in the PCB 20, the MLCC 10 should be manufactured to have a low thickness T. For this, a thin dielectric layer having a high dielectric constant is required. In the portion represented by A in FIG. 1b, the intervals between the internal electrodes 12 and 13 and the regions of the external electrodes 14 and 15 formed on the top and bottom surfaces of the capacitor body 11 are decreased, hence increasing parasitic capacitance Cp. As such, such parasitic capacitance Cp may cause an undesired parallel resonance frequency at a high frequency together with the ESL Ls.
Meanwhile, the MLCC 10 is disadvantageous in that because the areas of the external electrodes extending the top and bottom surfaces of the capacitor body 11 are small, it is difficult to embed the MLCC 10 in the PCB 20. For example, as in FIG. 2b, in the case in which the conductive via hole 23b is connected to the first external electrodes 14, the widths d2 of the upper regions of the first external electrodes 14 are small, and thus, an allowable range of variation of the diameter d1 of the via hole becomes narrow. To solve such a problem, the upper and lower regions of the first and second external electrodes 14 and 15 may be sufficiently enlarged. As a result, however, the parasitic capacitance Cp is increased, and as well, in more severe cases, short circuits between the external electrodes 14 and 15 may be caused.